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features ? floating channel designed for bootstrap operation ? fully operational to +500 v or +600 v ? tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for both channels ? 3.3 v logic compatible ? separate logic supply range from 3.3 v to 20 v ? logic and power ground 5v offset ? cmos schmitt-triggered inputs with pull-down ? cycle by cycle edge-triggered shutdown logic ? matched propagation delay for both channels ? outputs in phase with inputs description high and low side driver product summary v offset (irs2110) 500 v max. (irs2113) 600 v max. i o+/-2 a/2 a v out 10 v - 20 v t on/off (typ.) 130 ns & 120 ns delay matching (irs2110) 10 ns max. (irs2113) 20 ns max. www.irf.com 1 the irs2110/irs2113 are high voltage, high speed power mosfet and igbt drivers with independent high and low side referenced output channels. pro- prietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic in- puts are compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a high pulse current buffer stage designed for mini- mum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-chan- nel power mosfet or igbt in the high side configura- tion which operates up to 500 v or 600 v. irs2110( - 1, - 2,s)pbf irs2113( - 1, - 2,s)pbf (refer to lead assignments for correct pin configuration). this diagram shows electrical connec- tions only. please refer to our application notes and designtips for proper circuit board layout. typical connection preliminary packages 14-lead pdip irs2110 and irs2113 14-lead pdip (w/o lead 4) irs2110-1 and irs2113-1 16-lead pdip (w/o leads 4 & 5) irs2110-2 and irs2113-2 16-lead soic irs2110s and irs2113s data sheet no. pd60249 revb
preliminary www.irf.com 2 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation, the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at a 15 v differential. typical ratings at other bias conditions are shown in figs. 36 and 37. note 2: logic operational for v s of -4 v to +500 v. logic state held for v s of -4 v to -v bs . (refer to the design tip dt97-3) note 3: when v dd < 5 v, the minimum v ss offset is limited to -v dd. absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figs. 28 through 35. symbol definition min. max. units v b high side floating supply voltage (irs2110) -0.3 520 (note 1) (irs2113) -0.3 620 (note 1) v s high side floating supply offset voltage v b - 20 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage-0. 3 20 (note 1) v lo low side output voltage -0.3 v cc + 0.3 v dd logic supply voltage-0 .3 v ss +20 (note 1) v ss logic supply offset voltage v cc - 20 v cc + 0.3 v in logic input voltage (hin, lin, & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (fig. 2) 50 v/ns p d package power dissipation @ t a +25 c (14 lead dip) 1.6 (16 lead soic) 1.25 r thja thermal resistance, junction to ambient (14 lead dip) 75 (16 lead soic) 100 t j junction temperature 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 c/w w v c symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage (irs2110) note 2 500 (irs2113) note 2 600 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic supply offset voltage -5 (note 3) 5 v in logic input voltage (hin, lin & sd) v ss v dd t a ambient temperature -40 125 c v note 1: all supplies are fully tested at 25 v, and an internal 20 v clamp exists for each supply.
www.irf.com 3 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary symbol definition figure min. typ. max. units t est conditions t on turn-on propagation delay 7 ? 130 160 v s = 0 v t off turn-off propagation delay 8 ? 120 150 t sd shutdown propagation delay 9 ? 130 160 t r turn-on rise time 10 ? 25 35 t f turn-off fall time 11 ? 17 25 mt delay matching, hs & ls (irs2110) ? ? ? 10 turn-on/off (irs2113) ? ? ? 20 ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15 v, c l = 1000 pf, t a = 25 c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in fig. 3. symbol definition figure min. typ. max. units t est conditions v ih logic ?1? input voltage 12 9.5 ? ? v il logic ?0? input voltage 13 ? ? 6.0 v oh high level output voltage, v bias - v o 14 ? ? 1.2 i o = 0 a v ol low level output voltage, v o 15 ? ? 0.15 i o = 20 ma i lk offset supply leakage current 16 ? ? 50 v b =v s = 500 v/600 v i qbs quiescent v bs supply current 17 ? 125 230 i qcc quiescent v cc supply current 18 ? 180 340 i qdd quiescent v dd supply current 19 ? 15 30 i in+ logic ?1? input bias current 20 ? 20 40 v in = v dd i in- logic ?0? input bias current 21 ? ? 1.0 v in = 0 v v bsuv+ v bs supply undervoltage positive going 22 7.5 8.6 9.7 threshold v bsuv- v bs supply undervoltage negative going 23 7.0 8.2 9.4 threshold v ccuv+ v cc supply undervoltage positive going 24 7.4 8.5 9.6 threshold v ccuv- v cc supply undervoltage negative going 25 7.0 8.2 9.4 threshold i o+ output high short circuit pulsed current 26 2.0 2.5 ? v o = 0 v, v in = v dd pw 10 s i o- output low short circuit pulsed current 27 2.0 2.5 ? v o = 15 v, v in = 0v pw 10 s static electrical characteristics v bias (v cc , v bs , v dd ) = 15 v, t a = 25 c and v ss = com unless otherwise specified. the v in , v th, and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin, and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. v a v a v s = 500 v/600 v v in = 0 v or v dd
preliminary www.irf.com 4 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf functional block diagram lead definitions symbol de scription

v dd logic supply hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return
www.irf.com 5 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary lead assignments part number 14 lead pdip irs2110/irs2113 16 lead soic (wide body) irs2110s/ irs2113s 14 lead pdip w/o lead 4 irs2110-1/irs2113-1 16 lead pdip w/o leads 4 & 5 irs2110-2/irs2113-2
preliminary www.irf.com 6 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 5. shutdown waveform definitions ! ! ! "# 10 f 0.1 f v =15v cc 9 36 5 7 1 2 13 12 11 10 hin sd lin ho lo 0.1 f 10 f 10 f c l c l v b + - s v (0 to 500v/600v) 15v 10 f 0.1 f v =15v cc 9 36 5 7 1 2 13 12 11 10 ho 0.1 f output monitor 10kf6 10kf6 200 h 10kf6 100 f + irf820 hv = 10 to 500v/600v dv s >50 v/ns dt
www.irf.com 7 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) turn-off time (ns ) figure 8a. turn-off time vs. temperature figure 7a. turn-on time vs. temperature figure 7b. turn-on time vs. supply voltage figure 7c. turn-on time vs. v dd supply voltage figure 8b. turn-off time vs. supply voltage figure 8c. turn-off time vs. v dd supply voltage 0 50 10 0 15 0 200 250 -50 -25 0 25 50 75 100 125 temperature( o c) turn-on delay time (ns 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) turn-on delay time (ns ) 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature( o c) turn-off time (ns ) max. max. max. typ. typ. typ. typ. max. turn-on delay time (ns) turn-on delay time (ns) turn-off time (ns) turn-off time (ns) 0 50 100 150 200 250 02468101214161820 v dd supply voltage (v) m ax. typ . turn-on delay time (ns) 0 50 100 150 200 250 0 2 4 6 8 10 12 14 16 18 20 vslvlt (v) m ax. typ. v dd supply voltage (v) turn-off delay time (ns) turn-off delay time (ns)
preliminary www.irf.com 8 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf figure 9b. shutdown time vs. supply voltage figure 9a. shutdown time vs. temperature figure 9c. shutdown time vs. v dd supply voltage figure 10a. turn-on rise time vs. temperature figure 10b. turn-on rise time vs. voltage 0 20 40 60 80 100 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) max. typ. figure 11a. turn-off fall time vs. temperature 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature (c) turn-off fall time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) sd propagation delay (ns 0 50 100 150 200 250 10 12 14 16 18 20 v bias supply voltage (v) sd propagation delay (ns max. typ. max. typ. sd propagation delay (ns) turn-on rise time (ns) sd propagation delay (ns) turn-on rise time (ns) turn-off fall time (ns) temperature ( o c) 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 max. typ. 0 50 100 150 200 250 0 2 4 6 8 101214161820 v dd supply voltage (v) m ax. typ. shutdown delay time (ns)
www.irf.com 9 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary figure 11b. turn-off fall time vs. voltage 0 10 20 30 40 50 10 12 14 16 18 20 v bias supply voltage (v) turn-off fall time (ns) ma. typ. figure 12a. logic 1 input threshold vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic 1 input threshold (v) min. max figure 12b. logic 1 input threshold vs. voltage figure 13a. logic 0 input threshold vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic 0 input threshold (v) ma. min. figure 13b. logic 0 input threshold vs. voltage figure 14a. high level output vs. temperature 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) high level output voltage (v) ma. logic " 1" input threshold (v) 0 3 9 12 1 0 2 8 10 12 1 1 18 20 max. v dd logic supply voltage (v) 0 3 9 12 1 0281012111820 min . logic "0" input threshold (v) v dd logic supply voltage (v) turn-off all time (ns) logic 1 input threshold (v) logic 0 input threshold (v) logic 1 input threshold (v) logic 0 input threshold (v) igh leel output voltage (v)
preliminary www.irf.com 10 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf figure 14b. high level output vs. voltage figure 15a. low level output vs. temperature figure 15b. low level output vs. supply voltage figure 16a. offset supply current vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max. figure 17a. v bs supply current vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max. typ. 0.00 0.04 0.08 0.12 0.16 0.20 -50 -25 0 25 50 75 100 125 0.00 0.04 0.08 0.12 0.16 0.20 10 12 14 16 18 20 max. max. offset supply leakage current (
www.irf.com 11 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary figure 19b. v dd supply current vs. v dd voltage figure 20a. logic ?1? input current vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 max. typ. figure 17b. v bs supply current vs. voltage 0 100 200 300 400 500 10 12 14 16 18 20 max. typ. figure 18a. v cc supply current vs. temperature 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125 max. typ. figure 18b. v cc supply current vs. voltage 0 125 250 375 500 625 10 12 14 16 18 20 max. typ. figure 19a. v dd supply current vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 max. typ. 0 10 20 30 40 50 60 02468101214161820 v dd supply current (
preliminary www.irf.com 12 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf figure 21a. logic ?0? input current vs. temperature figure 21b. logic ?0? input current vs. v dd voltage figure 20b. logic ?1? input current vs. v dd voltage 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 max. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 max. typ. min. figure 22. v bs undervoltage (+) vs. temperature figure 23. v bs undervoltage (-) vs. temperature 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 max. typ. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 max. typ. min. figure 24. v cc undervoltage (+) vs. temperature l o g i c ? 1 ? i n p u t b i a s c u r r e n t ( m a ) 0 10 20 30 40 50 60 0 2 4 6 8 10 12 14 16 18 20 l o g i c ? 0 ? i n p u t b i a s c u r r e n t ( m a ) 0 1 2 3 4 5 0 2 4 6 8 10 12 14 16 18 20 l o g i c ? 1 ? i n p u t b i a s c u r r e n t ( m a ) l o g i c ? 0 ? i n p u t b i a s c u r r e n t ( m a ) l o g i c ? 0 ? i n p u t b i a s c u r r e n t ( m a ) v b s u n d e r v o l t a g e l o c k o u t + ( v ) v b s u n d e r v o l t a g e l o c k o u t - ( v ) v c c u n d e r v o l t a g e l o c k o u t + ( v ) v dd logic supply voltage (v) temperature ( o c) v dd logic supply voltage (v) temperature ( o c) temperature ( o c) temperature ( o c) pdf created with pdffactory trial version www.pdffactory.com
www.irf.com 13 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary figure 26b. output source current vs. voltage 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 o u t p u t s o u r c e c u r r e n t ( a ) min. typ. figure 27a. output sink current vs. temperature 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 o u t p u t s i n k c u r r e n t ( a ) min. typ. figure 27b. output sink current vs. voltage 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 o u t p u t s i n k c u r r e n t ( a ) min. typ. figure 28. irs2110/irs2113 t j vs. frequency (irfbc20) r gate = 33 w , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 320v 140v 10v figure 25. v cc undervoltage (-) vs. temperature 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) max. typ. min. figure 26a. output source current vs. temperature 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) o u t p u t s o u r c e c u r r e n t ( a ) min. typ. v c c u n d e r v o l t a g e l o c k o u t - ( v ) o u t p u t s o u r c e c u r r e n t ( a ) o u t p u t s o u r c e c u r r e n t ( a ) o u t p u t s i n k c u r r e n t ( a ) o u t p u t s i n k c u r r e n t ( a ) j u n c t i o n t e m p e r a t u r e ( o c ) temperature ( o c) temperature ( o c) temperature ( o c) v bias supply voltage (v) v bias supply voltage (v) frequency (khz) pdf created with pdffactory trial version www.pdffactory.com
preliminary www.irf.com 14 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf figure 29. irs2110/irs2113 t j vs. frequency (irfbc30) r gate = 22 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 p() 320v 140v 10v figure 30. irs2110/irs2113 t j vs. frequency (irfbc40) r gate = 15 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 320v 140v 10v figure 31. irs2110/irs2113 t j vs. frequency (irfpe50) r gate = 10 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 320v 140v 10v figure 32. irs2110s/irs2113s t j vs. frequency (irfbc20) r gate = 33 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 320v 140v 10v figure 33. irs2110s/irs2113s t j vs. frequency (irfbc30) r gate = 22 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 320v 140v 10v figure 34. irs2110s/irs2113s t j vs. frequency (irfbc40) r gate = 15 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 320v 140v 10v junction temperature ( o c) junction temperature ( o c) junction temperature ( o c) junction temperature ( o c) junction temperature ( o c) junction temperature ( o c) frequency (khz) frequency (khz) frequency (khz) frequency (khz) frequency (khz) frequency (khz)
www.irf.com 15 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary figure 35. irs2110s/irs2113s t j vs. frequency (irfpe50) r gate = 10 , v cc = 15 v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 p() 320v 140v 10v figure 36. maximum v s negative offset vs. v bs supply voltage -10.0 -8.0 -6.0 -4.0 -2.0 0.0 10 12 14 16 18 20 typ. figure 37. maximum v ss positive offset vs. v cc supply voltage 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 typ. junction temperature ( o c) v s offset supply voltage (v) v ss logic supply offset voltage (v) frequency (khz) v bs floating supply voltage (v) v cc fixed supply voltage (v)
preliminary www.irf.com 16 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf 01-6010 01-3002 03 (ms-001ac) 14-lead pdip case outlines 14-lead pdip w/o lead 4 01-6010 01-3008 02 (ms-001ac)
www.irf.com 17 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary 16-lead soic (wide body) 01 6015 01-3014 03 (ms-013aa) 16 lead pdip w/o leads 4 & 5 01-6015 01-3010 02
preliminary www.irf.com 18 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf carrier tape dimension for 16soicw code min max min max a 11.90 12.10 0.468 0.476 b 3 .9 0 4.1 0 0.15 3 0 .1 61 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 10.80 11.00 0.425 0.433 f 10.60 10.80 0.417 0.425 g 1 .5 0 n/a 0.05 9 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h n ot e : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 16-lead soic
www.irf.com 19 irs2110( - 1, - 2,s)pbf/irs2113( - 1, - 2,s)pbf preliminary order information 14-lead pdip irs2110pbf 14-lead pdip irs2110-1pbf 14-lead pdip irs2113pbf 14-lead pdip IRS2113-1PBF 16-lead pdip irs2110-2pbf 16-lead pdip irs2113-2pbf 16-lead soic irs2110spbf 16-lead soic irs2113spbf 16-lead soic tape & reel irs2110strpbf 16-lead soic tape & reel irs2113strpbf ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been qualified per industrial level data and specifications subject to change without notice 5/11/2006 leadfree part marking information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code s

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